The term substrate is to be understood in the general sense and may therefore encompass both monolayer and multilayer substrates of any desired type.
Although applicable to any desired semiconductor components, the present invention and the problem area on which it is based are explained with regard to dynamic random access memories (DRAMs) in silicon technology.
So-called one-transistor cells are used in dynamic random access memories (DRAMs). Said cells comprise a storage capacitor and a selection transistor (MOSFET), which connects the storage electrode to the bit line.
The storage capacitor is usually designed as a trench capacitor in the new memory generations. In particular, so-called STI (Shallow Trench Isolation) trenches are provided on the corresponding semiconductor memory chips, which trenches isolate different active regions from one another.
FIGS. 3a–c show the essential process stages of a method for the planarization of a semiconductor structure.
In FIG. 3a, reference symbol 1 designates a silicon semiconductor substrate into which capacitor trenches DT and shallow trench isolation trenches STI are introduced. The capacitor trenches DT are filled in a known manner with corresponding filling materials DFT, e.g. electrodes and dielectrics. Situated on the surface of the substrate 1 is a patterned hard mask HM, which has been opened at the locations of the capacitor trenches DT and isolation trenches STI. A TEOS oxide layer HDP to be planarized, which has depressions V1 and V2 at the locations of the trenches DT and STI, respectively, is provided over the resulting structure.
Firstly a preplanarization is carried out on this semiconductor structure. During this preplanarization, a preplanarization mask made of photoresist (not shown) is applied to the semiconductor structure by means of a photomask PM. In the known planarization method, the photomask PM contains open regions o above the capacitor trenches DT and above the planar periphery thereof and also closed regions c above the isolation trenches STI and the directly adjoining periphery thereof. If the structure of the photomask PM is then transferred to the photoresist (not shown) on the semiconductor structure by exposure, then, in the case of positive resist, a masking results at the locations of the closed regions c and a nonmasking results at the locations of the open regions o after the photoresist has been developed.
Afterward, the regions of the semiconductor structure which have been freed of the photoresist are etched selectively with respect to the masked regions, preferably by means of a dry etching method, which leads to the structure shown in FIG. 3b. During this dry etching step, it must be taken into consideration that residues of the TEOS oxide layer HDP still remain on the hard mask HM. The protection of the photoresist mask means that supporting regions SB remain in the periphery of the STI trenches, which supporting regions serve for avoiding a dishing effect in the isolation trenches STI if a chemical mechanical polishing step is subsequently carried out.
FIG. 3c shows the result of the planarization after said chemical mechanical polishing step. Said supporting structures SB prevent the dishing effect at the isolation trenches STI, as indicated by the planar surface. However, at the capacitor trenches DT, the pad nitride of the hard mask HM is attacked at the locations DE, which results in a very high degree of nonuniformity of the step height. These step height differences may extend up to 100 μm into adjacent regions.
FIG. 4 shows a known photomask which is used in the method for the planarization of a semiconductor structure in accordance with FIGS. 3a–c. 
FIG. 4 illustrates, in particular, a plan view of the photomask PM in accordance with FIG. 3a. The photomask PM has a first open region OB1 corresponding to a first active region AA, no capacitor trenches DT being provided in the active region AA. During the preplanarization etching, the TEOS oxide layer is etched back in said open region OB1.
Furthermore, the photomask PM has a second open region OB2 corresponding to a second active region AA′, the second active region AA′ having capacitor trenches DT. This region is shown in partial fashion in FIGS. 3a to c. 
Furthermore, the photomask PM has third open regions OB3 corresponding to further active regions AA″, which likewise comprise no capacitor trenches DT.
Finally, the photomask PM has a closed frame region GB, at which the underlying photoresist is not exposed. This closed region covers the isolation trenches STI in an overlapping manner in order thus to enable the formation of the supporting structures SB (cf. FIG. 3b) which can prevent the dishing effect in the isolation trenches STI.
This photomask PM has hitherto been generated by a computational algorithm which searches for active regions, such as e.g. AA, AA′, AA″, that is to say for non-STI regions which are larger than a predetermined limit value, typically a few μm2, and defines corresponding mask openings for them.
As stated, that entails the disadvantage of the dishing effect in the capacitor trenches DT, since these are not taken into account in the customary method. Moreover, it would be too laborious from the standpoint of the algorithm for each individual capacitor trench DT to be detected separately and provided with a corresponding supporting region.